Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC

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Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC

Marcello Coppola, Miltos D. Grammatikakis, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi, "Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC"
????: Study Temple-All kinds of Study Material Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC

CRC | ISBN: 1420044710 | September 17, 2008 | 288 pages | PDF | 4.2MB


Written by leading experts in the field, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC comprehensively examines the current state-of-the-art and future trends in multiprocessor system-on-chip (MPSoC), in particular network-on-chip (NoC) design. Incorporating simple methods with easy-to-understand examples, this book considers a wealth of important theoretical and practical topics, such as technological deep sub-micron effects, generic NoC components, topological properties, embeddings of common communication patterns, and system-level design. A complementary CD-ROM features a practical NoC training approach based on the award-winning OCCN environment.
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